The present invention relates to a fabrication technology of a semiconductor memory device, and more particularly, to a word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver.
A semiconductor memory device includes a word line, a bit line, and a memory cell. The word line is connected to a transistor having a gate receiving a boosted voltage (VPP). The boosted voltage (VPP) is generated by boosting an external power supply voltage (VDD) and thus its voltage level is higher than that of the power supply voltage (VDD). To drive the word line, the semiconductor memory device includes as many word line drivers as word lines.
FIG. 1 is a circuit diagram of a typical word line driver.
Referring to FIG. 1, the typical word line includes a first transistor PMOS1 enabling a word line WL in response to an activation of a main word line driving signal MWLB, a second transistor NMOS1 disabling the word line WL in response to a deactivation of the main word line driving signal MWLB, and a third transistor NMOS3 disabling the word line WL in response to an activation of a sub word line driving signal FXB.
The first transistor PMOS1 is connected to a word line driving signal FX having a level of a boosted voltage (VPP). The word line driving signal FX is a signal derived from the sub word line driving signal FXB. Specifically, the word line driving signal FX is generated by inverting the sub word line driving signal FXB through an inverter INV1. That is, the word line driver generates the word line driving signal FX by inverting the sub word line driving signal FXB, and drives the word line WL by using the word line driving signal FX.
FIG. 2 is a timing diagram of the signals MWLB, FXB and FX transferred to the word line driver.
Referring to FIG. 2, the main word line driving signal MWLB and the sub word line driving signal FXB are activated at the same time, while the word line driving signal FX is activated later than the main word line driving signal MWLB.
In this case, even though the main word line driving signal MWLB is transferred to the word line driver in order to drive the word line in an active operation, the word line driving signal FX actually driving the word line is activated late and thus the word line is driven when the word line driving signal FX is activated, not when the main word line driving signal MWLB is activated. That is, the time interval “A” is wasted.
Meanwhile, although the main word line driving signal MWLB and the sub word line driving signal FXB must be deactivated at the same time in a precharge operation, the deactivation timing of the word line driving signal FX is adjusted by deactivating the sub word line driving timing earlier in order to compensate the above-described time delay. Therefore, the first transistor PMOS1 and the third transistor NMOS2 maintain the driven state at the same time, thus forming an unnecessary direct current path. That is, an unnecessary current path is formed during the period “B”. This causes a fatal defect in a semiconductor memory device sensitive to a current waste.
FIG. 3 is a block diagram for explaining the reason why the word line driving signal FX is activated later than the main word line driving signal MWLB in the typical semiconductor memory device.
As illustrated in FIG. 3, the typical semiconductor memory device includes a plurality of memory cell blocks 10 and a plurality of word line driver blocks 11.
The memory cell block 10 includes a plurality of word lines WL1 to WLn, and the word line driver block 11 includes a plurality of word line drivers WLD1 to WLDn respectively connected to the word lines WL1 to WLn. Each of the word line drivers WLD1 to WLDn represents the word line driver illustrated in FIG. 1.
Furthermore, the word line driver block 11 receives the main word line driving signal MWLB and the sub word line driving signal FXB. In order to reduce the number of signal lines, one word line driving signal MWLB and one sub word line driving signal FXB are input to one word line driver block 11. Thus, the word line driving signal MWLB and the sub word line driving signal FXB are input to the word line drivers WLD1 to WLDn in sequence, starting from the first word line driver WLD1.
In particular, after the sub word line driving signal FXB is transferred up to the nth word line driver WLDn, it is output as the word line driving signal FX by the inverter INV1, and the word line driving signal FX is transferred to the first word line driver WLD1. That is, the generation of the word line driving signal FX includes the time taken until at least the sub word line driving signal FXB is transferred to all the word line drivers WLD1 to WLDn and passes through the inverter INV1 to generate the word line driving signal FX.
Therefore, considering that the sub word line driving signal FXB and the main word line driving signal MWLB are activated at the same time, the word line driving signal FX is activated later than the main word line driving signal MWLB by the above-described time.
As described above, the word line of the typical semiconductor memory device is driven when the word line driving signal FX is activated, not when the main word line driving signal MWLB is activated.
The delayed activation the word line driving signal FX degrades a RAS-to-CAS delay (tRCD) characteristic, one of parameters representing operation characteristics of the semiconductor memory device. The RAS-to-CAS delay (tRCD) means the time taken from the timing when the word line is driven by the application of the active command to the timing when the read strobe signal is activated in response to the read command. Therefore, there is a need for an improved technology that can solve the above-described limitation.